1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor memory device and method thereof.
2. Description of the Related Art
A semiconductor memory device including a plurality of access ports may be referred to as a multiport memory. A memory device having two access ports may further be referred to as a dual-port memory. A conventional dual-port memory may be, for example, an image processing video memory having a random access memory (RAM) port accessible in a random sequence and a serial access memory (SAM) port accessible in a serial sequence.
A dynamic random access memory (DRAM) may read from or write to a shared memory area through a plurality of access ports in a memory cell array not having an SAM port, and may be called a multipath accessible semiconductor memory device, as distinguished from a multiport memory.
Conventional portable electronic systems, such as a handheld multimedia player or handheld phone, a notebook computer, a PDA, etc., may include multiprocessor systems employing plural processors, as shown in FIG. 1, in order to obtain higher performance.
FIG. 1 is a block diagram of a conventional multiprocessor system within a portable communication device.
Referring to FIG. 1, a first processor 10 and a second processor 12 may be connected through a connection line L10, and a NOR memory 14 and a DRAM 16 may be coupled with the first processor 10 through buses B1-B3, and a DRAM 18 and a NAND memory 20 may be coupled with the second processor 12 through buses B4-B6. The first processor 10 may have a MODEM function for performing a modulation and demodulation of a communication signal and the second processor 12 may have an application function for dealing with communication data, games, etc. A NOR memory 14 having a NOR structure with a cell array configuration, and a NAND memory 20 having a NAND structure with a cell array configuration, may each be nonvolatile memories having a transistor memory cell with a floating gate. The nonvolatile memory may be adapted to store data in a “solid state”, such that data may be maintained even if a supply power is lost.
However, in a multi processor system such as illustrated in FIG. 1, DRAMs may correspond to and may be assigned to each processor, and lower-speed interfaces (e.g., UART, SPI, SRAM, etc.) may be used internally, such that a circuit complexity may be increased and an operational speed may be lower.
FIG. 2 is a block diagram of a conventional multiprocessor system including a semiconductor memory.
Referring to FIG. 2, a single DRAM 17 may be coupled to the first and second processors 10 and 12 through buses B1 and B2. The DRAM 17 may include two ports (e.g., one for each respective processor) to allow each processor 10 and 12 to access the DRAM 17 through each path in the structure of a multi processor system shown in FIG. 2. The two ports of the DRAM 17 may be connected to the first and second processors 10 and 12 via the buses B1 and B2, respectively.
FIG. 3 is a block diagram illustrating a conventional DRAM 1. In an example, the DRAM 1 may include a single port PO.
Referring to FIG. 3, the DRAM 1 may include a memory cell array having first to fourth banks 3, 4, 5 and 6, each corresponding to and connected with a row decoder 8 and a column decoder 7. An upper input/output sense amplifier and driver 13 may be operationally coupled to the first bank 3 or third bank 5 through multiplexer 11, 12, and a lower input/output sense amplifier and driver 13 may be operationally coupled to the second bank 4 or fourth bank 6 through multiplexer 14, 15.
Referring to FIG. 3, in an example, in selecting a memory cell of the first bank 3 and in reading data stored in the selected memory cell, an output procedure of the read data is as follows. A selected word line may be activated, and data of a memory cell may be sensed and amplified by a bit line sense amplifier and transferred to a local input/output line 9 according to an activation of corresponding column selection line CSL. Data transferred to the local input/output line 9 may be transferred to a global input/output line GIO by a switching operation of first multiplexer 21, and a second multiplexer 11 connected to global input/output line GIO may transfer data of the global input/output line GIO to the upper input/output sense amplifier and driver 13. The data may be sensed again and amplified by the upper input/output sense amplifier and driver 13 and may be output to a data output line L5 through a path unit 16.
Referring to FIG. 3, in another example, in reading data stored in a memory cell of the fourth bank 6, data may be output to an output terminal DQ, sequentially through a multiplexer 24, the multiplexer 14, the lower input/output sense amplifier and driver 13, the path unit 16 and the data output line L5. As described above, the DRAM 1 of FIG. 3 has a structure two banks share one input/output sense amplifier and driver, and is a single port memory an input/output of data is performed through one port PO. That is, the single-port DRAM 1 of FIG. 3 may be used within the system of FIG. 1, and may not be used within the multiprocessor system of FIG. 2 because the DRAM 1 includes a single port, and not dual ports.
FIG. 4 is a block diagram illustrating a conventional multiprocessor system 50.
Referring to FIG. 4, the multiprocessor system 50 may include a memory array 35 having first, second and third portions 33, 31 and 32, respectively. The first portion 33 of the memory array 35 may be accessed only by a first processor 70 through a port 37, and the second portion 31 may be accessed only by a second processor 80 through a port 38, and the third portion 32 may be accessed by each of the first and second processors 70 and 80. A size of the first and second portions 33 and 31 of the memory array 35 may vary based upon an operating load of the first and second processors 70 and 80, and the type of the memory array 35 may be either a memory type or disk storage type.
Referring to FIG. 4, the third portion 32 may be shared by the first and second processors 70 and 80 and the first and second portions 33 and 31, which may independently access the third portion 32 within the memory array 35. Assigning an appropriate read/write path control for respective ports may be an important design criterion. The bank address may indicate an address to select a given bank if a memory cell array is divided into a plurality of banks, and may be distinguished from a memory cell address to select a given memory cell from among a plurality of memory cells disposed in a matrix type. For example, if four memory banks (e.g., 00, 01, 10, 11) are included, four corresponding bank addresses (e.g., 00, 01, 10, 11) may be used to select from among the four memory banks.
In another example, even if the first processor writes data in a data input/output bit unit of 16 bits to the shared memory area through the first port, the second process may read data in a data input/output bit unit of 32 bits through the second port. Also, if the second processor writes data in a unit of 32 bits to the shared memory area, the first processor may read data in a unit of 16 bits. Thus, if the units of data input/output bit for respective ports are different, it may be difficult for the shared memory area to maintain data in a format compatible with both ports.